Random simulation-based verification is the main vehicle for integrated circuit (IC) design verification such as verification of System-on-Chip (SOC) and and/or an application-specific integrated circuit (ASIC) chip. The key indicators for the quality and completeness of this verification are coverage metrics, which can be categorized into two main classes: code coverage and functional coverage. Code coverage exploits the structure of register-transfer level (RTL) design to auto-generate coverage points of the IC design and hence make sure that all parts of the implementation of the IC design are exercised or visited by the random stimuli. Although some RTL simulator vendors provide built-in code coverage as well as state machine coverage generation tools, such auto-generated coverage information is not sufficient to show that all features of the IC design are exercised. Consequently, IC designers and verifiers almost always have to add functional coverage in their armor of coverage metrics.
Functional coverage captures the functionality of the IC design and provides an orthogonal view of random simulation quality by focusing on design features instead of the implementation of the IC design (as is the case of code coverage). Currently, the creation of functional coverage model(s) of the IC design is mostly a manual process, where verifiers study high-level English specification of the IC design and work with the IC designers to identify important design features. These design features are then translated into cover properties, cover points, and/or cross-coverage, etc., to create so-called coverage monitors, which can run in parallel with the IC design to monitor coverage of the key design features during simulation runs on the IC design. A coverage analysis process then processes the data generated by these coverage monitors to estimate coverage achieved through random simulation.
The manual identification of important design features and creation of the coverage monitors often suffers from various problems including but not limited to, outdated IC design specifications, errors in manual translation of the design features, and management of a monumental number of coverage points especially in the enormous protocol coverage space. For a non-limiting example, any industrial strength SOC protocol may have thousands of legally defined sequences, with many more illegal sequences, which leads to two undesirable strategies for coding functional coverage points: manually generating a coverage point for each of the thousands of legal transaction sequences, or crossing cover all state variables and manually excluding the enormous number of illegal sequences. Neither of these strategies works well for an evolving protocol and implementation and almost always leads to missing cases. Therefore, there is a need for an improved system and method to generate functional design coverage for IC design protocols.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.